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90308 ms pc/61199rm(ki) no.6183-1/15 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 LB11847 overview the LB11847 is a driver ic for stepping motors with pwm current control bipolar drive (fixed off time). a special feature of this ic is that v ref voltage is constant while the current can be set in 15 steps, allowing drive of motors ranging from 1-2 phase exciter types to 4w 1-2 phase excite r types. the current decay pattern can also be selected (slow decay, fast decay, mix decay) to increase th e decay of regenerative cu rrent at cho pping off, thereby improving response characteristics. this is especially useful for carriage and paper feed stepping motors in printers and similar applications where highprecision control and low vibrations are required. features ? pwm current control (fixed off time) ? load current digital selector (1-2, w1-2, 2w1-2, 4w1-2 phase exciter drive possible) ? selectable current decay pattern (s low decay, fast decay, mix decay) ? simultaneous on prevention function (feedthrough current prevention) ? noise canceler ? built-in thermal shutdown circuit ? built-in logic low-voltage off circuit specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit motor supply voltage v bb 50 v output peak current i opeak t w 20 s 1.75 a output continuous current i o max 1.5 a logic supply voltage v cc 7.0 v logic input voltage range v in -0.3 to v cc v emitter output voltage v e 1.0 v ta = 25 c 3.0 w allowable power dissipation pd max with heat sink 20 w operating temperature topr -20 to +85 c storage temperature tstg -55 to +150 c monolithic digital ic pwm current control type stepping motor driver orderin g numbe r : en6183a stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LB11847 no.6183-2/15 allowable operating conditions at ta = 25 c parameter symbol conditions ratings unit motor supply voltage range v bb 10 to 45 v logic supply voltage range v cc 4.75 to 5.25 v reference voltage range v ref 0.0 to 3.0 v electrical characteristics at ta = 25 c, v bb = 45v, v cc = 5v, v ref = 1.52v ratings parameter symbol conditions min typ max unit output block i bb on 2.3 3.5 5.0 ma output stage supply voltage i bb off 0.5 0.8 1.1 ma v o (sat) 1 i o = +1.0a, sink 1.2 1.6 v v o (sat) 2 i o = +1.5a, sink 1.5 1.9 v v o (sat) 3 i o = -1.0a, source 1.9 2.2 v output saturation voltage v o (sat) 4 i o = -1.5a, source 2.2 2.4 v i o (leak) 1 v o = v bb , sink 50 a output leak current i o (leak) 2 v o = 0v, source -50 a output sustain voltage v sus l = 15 mh, i o = 1.5a, guaranteed design value 45 v logic block i cc on i 4 = 2.0v, i 3 = 2.0v, i 2 = 2.0v, i 1 = 2.0v 19.5 26 36.5 ma logic supply current i cc off enable = 2.0v 10.5 15 19.5 ma v ih 2.0 v input voltage v il 0.8 v i ih v ih = 2.0v 100 a input current i il v il = 0.8v -10 a i 4 = 2.0v, i 3 = 2.0v, i 2 = 2.0v, i 1 = 2.0v 0.470 0.50 0.525 v i 4 = 2.0v, i 3 = 2.0v, i 2 = 2.0v, i 1 = 0.8v 0.445 0.48 0.505 v i 4 = 2.0v, i 3 = 2.0v, i 2 = 0.8v, i 1 = 2.0v 0.425 0.46 0.485 v i 4 = 2.0v, i 3 = 2.0v, i 2 = 0.8v, i 1 = 0.8v 0.410 0.43 0.465 v i 4 = 2.0v, i 3 = 0.8v, i 2 = 2.0v, i 1 = 2.0v 0.385 0.41 0.435 v i 4 = 2.0v, i 3 = 0.8v, i 2 = 2.0v, i 1 = 0.8v 0.365 0.39 0.415 v i 4 = 2.0v, i 3 = 0.8v, i 2 = 0.8v, i 1 = 2.0v 0.345 0.37 0.385 v i 4 = 2.0v, i 3 = 0.8v, i 2 = 0.8v, i 1 = 0.8v 0.325 0.35 0.365 v i 4 = 0.8v, i 3 = 2.0v, i 2 = 2.0v, i 1 = 2.0v 0.280 0.30 0.325 v i 4 = 0.8v, i 3 = 2.0v, i 2 = 2.0v, i 1 = 0.8v 0.240 0.26 0.285 v i 4 = 0.8v, i 3 = 2.0v, i 2 = 0.8v, i 1 = 2.0v 0.195 0.22 0.235 v i 4 = 0.8v, i 3 = 2.0v, i 2 = 0.8v, i 1 = 0.8v 0.155 0.17 0.190 v i 4 = 0.8v, i 3 = 0.8v, i 2 = 2.0v, i 1 = 2.0v 0.115 0.13 0.145 v sensing voltage v e i 4 = 0.8v, i 3 = 0.8v, i 2 = 2.0v, i 1 = 0.8v 0.075 0.09 0.100 v reference current i ref v ref = 1.5v -0.5 a cr pin current i cr cr = 1.0v -4.6 -1.0 ma md pin current i md md = 1.0v, cr = 4.0v -5.0 a decay pin current low i decl v dec = 0.8v -10 a decay pin current high i dech v dec = 2.0v 5 a thermal shutdown temperature tsd 170 c logic on voltage l vsd 1 3.35 3.65 3.95 v logic off voltage l vsd 2 3.20 3.50 3.80 v l vsd hysteresis width l vsd 0.065 0.15 0.23 v
LB11847 no.6183-3/15 package dimensions unit : mm (typ) 3147c pin assignment sanyo : dip28h(500mil) 1 14 28 15 0.4 0.6 4.0 4.0 26.75 20.0 r1.7 8.4 (1.81) 1.78 1.0 12.7 11.2 pd max ? ta 0 20 15 10 5 25 ? 20 80 20.0 10.4 1.56 3.0 60 20 40 0 100 independent ic with an arbitrary large heat sink ambient temperature, ta ? c allowable power dissipation, pd max ? w 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 v cc phase1 enable1 i a 1 i a 2 i a 3 i a 4 i b 4 i b 3 i b 2 i b 1 enable2 phase2 gnd md v ref 1 cr1 e1 decay1 out a out a out b out b decay2 e2 cr2 v ref 2 v bb LB11847 top view
LB11847 no.6183-4/15 pin function pin number pin name function descripyion 1 md sets the off time for fast mode and slow mode in mix decay. setting input range: 4v to 1.5v 2 13 v ref 1 v ref 2 output set current reference supply pins. setting voltage range: 0v to 3v 3 12 cr1 cr2 output off time setting pins for switching operation. 4 11 e1 e2 pins for controlling the set current with sensing resistor re. 5 10 decay1 decya2 slow mode/fast mode selector pins. slow decay : h fast decay : l 6 7 8 9 out a out a out b out b output pins. 14 v bb output stage supply voltage pin. 15 gnd ground pin. 27 16 phase1 phase2 output phase selector input pins. 26 17 enable1 enable2 output on/off setting input pins. 22, 23 24, 25 21, 20 19, 18 i a 4, i a 3 i a 2, i a 1 i b 4, i b 3 i b 2, i b 1 output set current digital input pins. 15-stage voltage setting. 28 v cc logic block supply voltage pin. truth table phase enable out a out a h l h l l l l h - h off off set current truth table i a 4 i a 3 i a 2 i a 1 set current i out current ratio (%) 1 1 1 1 11.5/11.5 v ref /3.04re = i out 100 1 1 1 0 11.0/11.5 v ref /3.04re = i out 95.65 1 1 0 1 10.5/11.5 v ref /3.04re = i out 91.30 1 1 0 0 10.0/11.5 v ref /3.04re = i out 86.95 1 0 1 1 9.5/11.5 v ref /3.04re = i out 82.61 1 0 1 0 9.0/11.5 v ref /3.04re = i out 78.26 1 0 0 1 8.5/11.5 v ref /3.04re = i out 73.91 1 0 0 0 8.0/11.5 v ref /3.04re = i out 69.56 0 1 1 1 7.0/11.5 v ref /3.04re = i out 60.87 0 1 1 0 6.0/11.5 v ref /3.04re = i out 52.17 0 1 0 1 5.0/11.5 v ref /3.04re = i out 43.48 0 1 0 0 4.0/11.5 v ref /3.04re = i out 34.78 0 0 1 1 3.0/11.5 v ref /3.04re = i out 26.08 0 0 1 0 2.0/11.5 v ref /3.04re = i out 17.39 * current ratio (%) is the calculated set current value. current decay switching truth table current decay mode decay pin md pin output chopping slow decay h l upper-side chopping fast decay l l dual-side chopping mix decay l 4v to 1.5v input voltage setting cr voltage > md : dual-side chopping cr voltage < md : upper-side chopping
LB11847 no.6183-5/15 block diagram control logic circuit thermal shutdown circuit control logic circuit cuttent selector circuit cuttent selector circuit one-shot multi- blanking circuit one-shot multi- blanking circuit md phase1 decay1 enable1 i a 1 i a 2 i a 3 i a 4 v ref 1 gnd v cc out b out b v bb out a out a phase2 decay2 enable2 i b 1 i b 2 i b 3 i b 4 v ref 2 cr1 e1 e2 cr2
LB11847 no.6183-6/15 sequence table phase a phase b no. i a 4 i a 3 i a 2 i a 1 ena1 pha1 i out i b 4i b 3i b 2i b 1 ena2 pha2 i out phase 1-2 phase w1-2 phase 2w1-2 phase 4w1-2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 100% 100 100 95.65 91.30 86.95 82.61 78.26 73.91 69.56 60.87 52.17 43.48 34.78 26.08 17.39 0 17.39 26.08 34.78 43.48 52.17 60.87 69.56 73.91 78.26 82.61 86.95 91.30 95.65 100 100 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0% 17.39 26.08 34.78 43.48 52.17 60.87 69.56 73.91 78.26 82.61 86.95 91.30 95.65 100 100 100 100 100 95.65 91.30 86.95 82.61 78.26 73.91 69.56 60.87 52.17 43.48 34.78 26.08 17.39 * : iout percentage (%) is the calculated setting value.
LB11847 no.6183-7/15 switch timing chart during pwm drive output pin rc pin output pin e pin output pin rc pin output pin e pin t n switching waveform switching waveform noise spike fast decay slow decay (upper-side chopping) decay pin : high decay pin : high md pin : low md pin : low
LB11847 no.6183-8/15 t on : output on time t off : output off time t m : fast decay time in mix decay mode t n : noise cancelling time mix decay logic setting decay pin : l md pin : 1.5v to 4.0v voltage setting cr voltage and md pin voltage are compared to select dual-side chopping or upper-side chopping. cr voltage > md pin voltage: dual-side chopping cr voltage < md pin voltage: top-side choppinng t m t n switching wavwform output pin rc pin output pin e pin mix decay t off t on noise spike
LB11847 no.6183-9/15 slow decay current path regenerative current during upper-side transistor switching operation current path in fast decay mode on constant sensing voltage comparato r current path at output on regenerative circuit when upper-side transistor is off sensing voltage comparato r current path at output on current path in fast decay mode on out a sbd sbd re out a v bb off on on off out a sbd sbd re v bb off out a
LB11847 no.6183-10/15 composite vectors of set current (1 step normalized to 90 ) no. rotation angles composite vectors 0 0 0 100.0 1 1 9.87 101.5 2 2 14.6 103.35 3 3 20.0 101.78 4 4 25.5 101.12 5 5 30.96 101.4 6 6 36.38 102.61 7 7 41.63 104.7 8 8 45.0 104.5 9 9 48.37 104.7 10 10 53.62 102.61 11 11 59.04 101.4 12 12 64.5 101.12 13 13 70.0 101.78 14 14 75.4 103.35 15 15 80.13 101.5 16 16 90.0 100.0 * rotation angle and compos ite spectrum are calculated values. phase b i out phase a i out 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sequence no.
LB11847 no.6183-11/15 set current waveform model i out i out phase a phase b phase1 phase2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LB11847 no.6183-12/15 sample application circuit notes on usage 1. external diodes because this ic uses upper-side transi stor switching in slow decay mode an d dual-side transistor switching in fast decay mode, it requires external diodes between the out pins and ground for the regenerative current during switching off. use schottky ba rrier diodes with low vf. 2. v ref pin because the v ref pin serves for input of the set current reference voltage, precautions against noise must be taken. the input voltage range is 0 to 3.0v. 3. gnd pin the ground circuit for this ic must be designed so as to allow for high-current switching. blocks where high current flows must use low-impedance patterns and must be removed from small-signal lines. especially the ground connection for the sensing resistor re at pin e, and the ground connection for the schottky barrier diodes should be in close proximity to the ic ground. the capacitors between v cc and ground, and v bb and ground should be placed close to the v cc and v bb pins, respectively. 1.5v to 4.0v voltage setting logic input 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc phase1 enable1 i a 1 i a 2 i a 3 i a 4 i b 4 i b 3 i b 2 i b 1 enable2 phase2 gnd md v ref 1 cr1 e1 decay1 out a out a out b out b decay2 e2 cr2 v ref 2 v bb 10 f 5v 470pf 470pf 47 f 42v 0.51 0.51 15k 15k 1.5v sbd sbd sbd sbd l l LB11847
LB11847 no.6183-13/15 4. simultaneous on prevention function this ic incorporates a circuit to prevent feedthrough curr ent when phase switching. for reference, the output on and off delay times at phase and enable switching are given below. reference data * typical value sink side source side on delay time 1.9 s 2.2 s phase switching (low high) off delay time 0.8 s 1.8 s on delay time 1.4 s 1.7 s phase switching (high low) off delay time 0.9 s 1.35 s on delay time 2.15 s 2.75 s enable switching off delay time 1.2 s 5.8 s 5. noise canceler this ic has a noise canceling function to prevent malfunction due to noise spikes generated when switching on. the noise cancel time t n is determined by internal resistance of the cr pi n and the constant of th e externally connected cr components. the constant also determines the switching off time. figure 1 shows the internal configuration at the cr pin, and figure 2 shows the cr pin constant setting range. equation when logic voltage v cc = 5v cr pin voltage e1 = v cc ? r/(r1+r2+r) [v] noise cancel time t n (r1+r2) ? c ? 1n {(e1-1.5)/(e1-4.0)} [s] switching off time t off ?r ? c ? 1n (1.5/e1) [s] internal resistance at cr pin : r1 = 1k , r2 = 300 (typ.) *the cr constant setting range in figure 2 on page 16 is given for reference. it applies to a switching off time in the range from 8 to 100 s. the switching time can also be made higher than 100 s. however, a capacitor value of more than several thousand pf will result in longer noise can celing time, which can cause the output current to become higher than the set current. the longer switching off time resu lts in higher output current ripple, causing a drop in average current and rotation efficiency. when keeping the switching off time within 100 s, it is recommended to stay within the cr constant range shown in figure 2. internal configuration at cr pin figure 1 cr pin e1 one-shot multi-blanking time circuit v cc line r:15k c:470pf 300 r1 r2 1k
LB11847 no.6183-14/15 switching off time and cr setting range (t off time : approx. 8 to 100 s) figure 2 50k 0 100k 0 t off time : 30 s t off time : 50 s t off time : 100 s r [ ] 1000 2000 3000 c [pf]
LB11847 ps no.6183-15/15 0 10 20 30 40 0.4 0.8 1.2 1.6 2.0 2.4 50 045 3 2 16 1.6 2.0 1.2 0.8 0.4 7 output on source side [typical value] sink side [typical value] output off output on output off i cc -- v cc logic supply voltage, v cc ? mv output stage supply voltage, v bb ?v logic supply current, i cc ?ma 0 2.8 0.4 0.8 1.2 1.6 2.0 2.4 0 2.8 0 2.4 1.6 2.0 1.2 0.8 0.4 0 2.4 v o(sat) -- i o v o(sat) -- i o output current, i o ?a output saturation voltage, v o(sat) ?v 0 1 2 3 4 5 040 30 20 10 50 60 i bb -- v bb output current, i o ?a output stage supply current, i bb ?ma output saturation voltage, v o(sat) ?v logic supply voltage : i a 1, 2, 3, 4 pha, ena = v cc typical value logic supply voltage : i a 1, 2, 3, 4 pha, ena = v cc typical value on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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